WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: The AMD IOHUB Team (part of the NBIO organization) is looking for an ASIC Design Verification Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP verification starting from helping to create a verification architecture, defining test plans, verification environment development, and verification closure/sign-off. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: Strong analytical thinking and problem-solving skills, excellent attention to detail. Possesses good teamwork, communication and interpersonal skills A self-starter and able to independently drive tasks to completion Enjoys working in a fast-paced, multi-project team environment using state of the art tools and technology Possesses a continuous improvement mind-set KEY RESPONSIBILITIES: Collaborate with IP architects to come up with verification architecture and development plans Participate in verification of complex IP blocks and take end-to-end ownership of key features for all projects Work on test plans, verification environment development, regression, and coverage closure Develop modifying and maintaining VIP, libraries, verification environments, testcases (random and directed) using System Verilog/UVM/SystemC Triaging and Debugging Regressions Analyzing code and functional coverage Deploying industry-leading verification methodologies such as UVM and formal Verification Reproducing functional bugs found in Post-Silicon in dynamic simulation and/or formal verification environments Conducting and participating in code reviews Develop and maintain scripts and tools to continuously improve in engineering infrastructure, methodology and execution PREFERRED EXPERIENCE: Strong ASIC verification experience Strong understanding of digital design and computer architecture Proficient in Verilog, System Verilog, C/C++, UVM, OOP, and working in Linux and Windows environments ASIC design knowledge and be able to debug System Verilog RTL code using simulation tools Experience in security verification would be an asset ACADEMIC CREDENTIALS: BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science. LOCATION: Vancouver, BC; Markham, Ontario, CA #LI-SL3 #Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.