WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER THE ROLE: The Infinity Fabric transport layer verification team is looking for an experienced Formal Verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across Client, Server, Graphics, and Semi-Custom markets. Our growing team needs additional senior engineering experience to help us enhance our configurable testbench and to mentor junior engineers. THE PERSON: The preferred candidate will have proven experience verifying complex design blocks using Formal Methodologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification. KEY RESPONSIBILITIES: Identify formal friendly modules/features across Data Fabric unit/subsystem and work with different stake holders in getting a thorough understanding of microarch/high level spec and get clarification (if any). Evaluate cross-feature/cross-unit dependency impact. Populate detailed testplan (planned checks, abstraction, coverage) post feature analysis and get it reviewed & incorporate feedback. Create Formal Testbench with assertions/assumptions with necessary level of abstraction in place to verify a complete feature. Debug failures to root cause issues/fix constraints, deal with tool issues efficiently in collaboration with concerned AE from Synopsys/Cadence. On a need basis, work on Post-Si bug recreation. On a need basis, work on Flow automation related to Formal flow. PREFERRED EXPERIENCE: 10+ years of experience on Formal verification on Complex IP's. Proficiency in overall Formal Verification methodology with tools like (VC-FORMAL/JASPER). Proficiency in creating testplans, building formal testbenches from scratch. Good understanding about computer architecture/microarchitecture and ability to deal with complex sequential logic and datapath. Good understanding of Verilog, System Verilog, SVA. Some knowledge of shell/perl/python scripting is a plus. Should have leadership quality, quick thinker, pro-active, adaptable & outspoken/approachable. Must communicate well both written and orally. Must be well-organized and should be able to multitask well with due diligence on closing his/her tasks. ACADEMIC CREDENTIALS: Bachelor’s or master’s degree in Electronics or Electrical or Computer engineering #LI-ST1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.