HW/SW Co-design Engineer

About the Team

Our mission at OpenAI is to discover and enact the path to safe, beneficial AGI. To do this, we believe that many technical breakthroughs are needed in generative modeling, reinforcement learning, large scale optimization, active learning, among other topics.

The Research Platform team builds robust and scalable software to support our research efforts. It also offers core development services for mission critical goals and applications. In the Kernels team, we write Kernels for GPUs, we build a compiler to support important AI accelerators and we help with HW/SW co-design of future AI accelerators. 

About the Role

As a Research Engineer, you will help build AI systems that can perform previously impossible tasks or achieve outstanding levels of performance. This requires good engineering (for example designing, implementing, and optimizing state-of-the-art AI models), writing bug-free machine learning code (surprisingly difficult!), and building the science behind the algorithms employed. In all the projects this role pursues, the ultimate goal is to push the field forward.

As a Research Engineer for HW/SW co-design, you will co-design future hardware from different vendors for programmability and performance. You will work with our kernel, compiler and ML developers to understand their needs related to ML techniques, algorithms, numerical approximations, programming expressivity and compiler optimizations. You will evangelize these constraints with various vendors to develop future hardware architectures amenable for efficient training and inference. If you are excited about maximizing HBM bandwidth, optimizing for low arithmetic intensity, expressive SIMD ISA, low-precision formats, optimizing for memory hierarchies, simulating workloads at various resolutions of the hardware and evangelizing these ideas with hardware engineers, this is the perfect opportunity!

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role, you will:

• Work with hardware vendors to help co-design their future hardware for programmability and performance
• Assist hardware vendors in developing optimal kernels and add support for it in our compiler
• Develop performance estimates for critical kernels for different hardware configurations 
• Work with ML engineers, kernel engineers and compiler developers to understand their vision and needs from high performance accelerators
• Manage communication and coordination with internal and external engagements

You might thrive in this role if you

• Have a deep understanding of GPU and/or other AI accelerators
• Have good experience with CUDA or a related accelerator programming language
• Have experience driving ML accuracy with low precision formats
• Able to actively collaborate with ML engineers, kernel writers and compiler developers
• Have 3+ years of relevant industry experience
• Get a great deal of satisfaction with aligning future hardware with a well established HPC infrastructure

These attributes are nice to have

• PhD in Computer Science and Engineering with a specialization in Computer Architecture, Parallel Computing. Compilers or other Systems
• Are a strong coder with excellent skills in C/C++ and Python
• Experience working with hardware developers
• Experience building compilers
• Good understanding of LLMs and challenges related to their training and inference 

Benefits and Perks

• Medical, dental, and vision insurance for you and your family
• Mental health and wellness support
• 401(k) plan with 4% matching
• Unlimited time off and 18+ company holidays per year
• Paid parental leave (20 weeks) and family-planning support
• Annual learning & development stipend ($1,500 per year)