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MTS SILICON DESIGN ENGINEER
Bachelors/Masters in Electrical engineering
Relevant experience : 8+ years
AMD – Adaptive and Embedded Computing Group(AECG) Processor Design(PS) SoC design group strive to get best in Industry class features and productize them. The job requires a candidate who is not limited by the boundary and willing to push the bar always. We are looking for an RTL lead role that require 8+ yrs SoC/ASIC design experience in Industry.
The role of RTL Lead is to develop Microarchitecture document and lead integration of IO peripheral sub-system for state of the art 7nm SoC products. The successful candidate will be design owner for subsystem/large IPs with multiple IP and interconnect including any custom SoC logic requirements(clocks/resets). He/she should be thorough conversant with std-cell based SoC design methodology and timing closure activities with Physical design team.
The knowledge of AXI based processing system and integration of Ips like like eMMC, Ethernet, USB, PCIE are required for this role. The candidate is expected to have very good understanding of clocking and timing constraints design and have worked for at least one SoC project for timing closure.
- The candidate should be proficient in SOC subsystem microarchitecture development from system level architecture document
- Should have done SoC level integration of IP like eMMC, PCIE, USB, Ethernet etc
- Should know timing constraints for Synthesis/STA for an SoC
- Should be aware of SoC integration and quality checks like Lint, CDC, RDC, Gate level CDC
- Should have worked for low power design with UPF
The successful candidate will be point of contact for the IO subsystem and drive RTL relates issues and resolutions to larger cross-functional teams. It’s assumed that RTL lead will understand the block well and able to mentor technically about 2 engineers working for the same subsystem.
#LI-SK4
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
MTS SILICON DESIGN ENGINEER
Bachelors/Masters in Electrical engineering
Relevant experience : 8+ years
AMD – Adaptive and Embedded Computing Group(AECG) Processor Design(PS) SoC design group strive to get best in Industry class features and productize them. The job requires a candidate who is not limited by the boundary and willing to push the bar always. We are looking for an RTL lead role that require 8+ yrs SoC/ASIC design experience in Industry.
The role of RTL Lead is to develop Microarchitecture document and lead integration of IO peripheral sub-system for state of the art 7nm SoC products. The successful candidate will be design owner for subsystem/large IPs with multiple IP and interconnect including any custom SoC logic requirements(clocks/resets). He/she should be thorough conversant with std-cell based SoC design methodology and timing closure activities with Physical design team.
The knowledge of AXI based processing system and integration of Ips like like eMMC, Ethernet, USB, PCIE are required for this role. The candidate is expected to have very good understanding of clocking and timing constraints design and have worked for at least one SoC project for timing closure.
- The candidate should be proficient in SOC subsystem microarchitecture development from system level architecture document
- Should have done SoC level integration of IP like eMMC, PCIE, USB, Ethernet etc
- Should know timing constraints for Synthesis/STA for an SoC
- Should be aware of SoC integration and quality checks like Lint, CDC, RDC, Gate level CDC
- Should have worked for low power design with UPF
The successful candidate will be point of contact for the IO subsystem and drive RTL relates issues and resolutions to larger cross-functional teams. It’s assumed that RTL lead will understand the block well and able to mentor technically about 2 engineers working for the same subsystem.
#LI-SK4