WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Project CAD and STA methodology and optimization team, you will work on new signoff design flows and methodology, automation and regression to release quality instructions to Project execution team and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success. . THE PERSON: A successful person in this role would be able to work in a collaborative team environment working with other business units, central methodology team driving the group signoff and solving the critical issues with vendor. Strong self-driving ability, should have excellent communication skills (both written and oral) KEY RESPONSIBILITIES: Drive the common STA methodology in the business unit Work and collaborate with different business units, CAD and central methodology team to drive the requirement Automation to refine and improve design signoff requirement and dashboarding Ability to organize and present complex technical information in a crisp and concise manner. Interact with other PPA (equivalent) teams internal to AMD Identify best practices across AMD and industry to update and improve flow/project settings To increase the competitiveness of each stage in AMD design flow Ability to work with multi-level functional teams across various geographies. Highly organized, strong affinity for automation and prioritization. PREFERRED EXPERIENCE: 8+ year or more experience design signoff closure Timing closure experience at SoC and block level Technical depth in STA, High freq interface closure in hierarchical STA. Multi voltage closure Timing ECO flow Hyperscale, Yield analysis PnR and STA signoff correlation drive and convergence Strong at SDC coding and debug skills Drive new requirements and methodology to aid timing closure at SoC Identify the gaps and support flows Strong in scripting, Scripting language experience: TCL, Perl, Python, Makefile. Drive team towards common requirements and flows Experienced in deploying and implementing ML techniques and algorithms in physical design. Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification Experience with different tools from various vendors - Synopsys, Cadence and Mentor. AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RP1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.