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MTS Product Engineer
The Product Engineer position is in the Customer Enablement and Success group, located in Hyderabad, Telangana, India, for an experienced application engineer to focus on FPGA & ACAP design methodologies, compilation flows, design closure ease-of-use, tools specification, validation, documentation and key customers support. As a member of a highly seasoned Product Development Engineering team, the successful candidate will work closely with several R&D teams, internal application design teams and tier-1 customers to improve the user experience and productivity and enable the next generation of high performance computing designs across the UltraScale and Versal ACAP device families. Daily activities will include the following duties:
- Own a Vivado product area and become the future team champion to work on high impact projects and with key customers.
- Drive critical customer escalations to closure and contribute to new technologies rollout.
- Contribute to triaging reported issues in several Vivado product areas, such as design entry, NoC and IP design flows, compilation, and help engineering address them effectively.
- Actively explore innovative methodologies and their impact on flow and design practices for the new 7nm Versal ACAP family.
- Work closely with AMD Business Units (Data Center, Wired, Wireless, Emulation & Prototyping, Test Equipment) to improve their designs, products and customer experience.
- Develop and deliver training materials on new features and methodologies.
- Stay current with and propose the internal use of industry approaches, algorithms, and practices
Education and Experience Requirements
MS or equivalent work experience in Electrical Engineering or similar technology area, with minimum 8 years of relevant experience.
- Customer Awareness: Has excellent working knowledge of RTL-based design flows and expectations.
- Product Knowledge: Has good working knowledge of the entire FPGA or ASIC design process and tool flow, with intermediate-to-advanced understanding in timing analysis and closure. Scripting experience (Tcl, Perl, Python) is desired.
- Design Enablement: Has good understanding of design methodologies for system design, AXI protocol, network-on-chip, design closure.
- Problem Solving: Ability to handle and solve complex system level issues.
- Technical Communication: Can simplify and communicate even the most complex subjects, making options, tradeoffs, and impact clear. Can report out to management in a concise and actionable manner.
- Teamwork: Able to work with several teams across sites and domains with a positive attitude under variable workloads.
#LI-MK1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
MTS Product Engineer
The Product Engineer position is in the Customer Enablement and Success group, located in Hyderabad, Telangana, India, for an experienced application engineer to focus on FPGA & ACAP design methodologies, compilation flows, design closure ease-of-use, tools specification, validation, documentation and key customers support. As a member of a highly seasoned Product Development Engineering team, the successful candidate will work closely with several R&D teams, internal application design teams and tier-1 customers to improve the user experience and productivity and enable the next generation of high performance computing designs across the UltraScale and Versal ACAP device families. Daily activities will include the following duties:
- Own a Vivado product area and become the future team champion to work on high impact projects and with key customers.
- Drive critical customer escalations to closure and contribute to new technologies rollout.
- Contribute to triaging reported issues in several Vivado product areas, such as design entry, NoC and IP design flows, compilation, and help engineering address them effectively.
- Actively explore innovative methodologies and their impact on flow and design practices for the new 7nm Versal ACAP family.
- Work closely with AMD Business Units (Data Center, Wired, Wireless, Emulation & Prototyping, Test Equipment) to improve their designs, products and customer experience.
- Develop and deliver training materials on new features and methodologies.
- Stay current with and propose the internal use of industry approaches, algorithms, and practices
Education and Experience Requirements
MS or equivalent work experience in Electrical Engineering or similar technology area, with minimum 8 years of relevant experience.
- Customer Awareness: Has excellent working knowledge of RTL-based design flows and expectations.
- Product Knowledge: Has good working knowledge of the entire FPGA or ASIC design process and tool flow, with intermediate-to-advanced understanding in timing analysis and closure. Scripting experience (Tcl, Perl, Python) is desired.
- Design Enablement: Has good understanding of design methodologies for system design, AXI protocol, network-on-chip, design closure.
- Problem Solving: Ability to handle and solve complex system level issues.
- Technical Communication: Can simplify and communicate even the most complex subjects, making options, tradeoffs, and impact clear. Can report out to management in a concise and actionable manner.
- Teamwork: Able to work with several teams across sites and domains with a positive attitude under variable workloads.
#LI-MK1