WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ PMTS ASIC Verification Engineer The ideal candidate is one, who has a proven track record on driving strategies and successful verification execution on Block level and System level verification of high-performance IPs and/or SOC designs. Qualifications: Experience (15+ years) in Technically leading a team and working with cross-functional teams, planning inter-locks with dependent teams, pre-empting the risks and having a plan to mitigate. Experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify high performance IPs and/or SOC designs. Proven track record on driving strategies and successful verification execution on high performance IPs and/or SOC designs. Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools, and infrastructure for high performance-IP and/or VLSI designs is a plus. · Experience with FPGA programming and software is a plus. · Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) are a plus. · Experience with gate level simulation, power aware verification, reset verification, contention checking is a plus. · Prior experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-MK1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
PMTS ASIC Verification Engineer The ideal candidate is one, who has a proven track record on driving strategies and successful verification execution on Block level and System level verification of high-performance IPs and/or SOC designs. Qualifications: Experience (15+ years) in Technically leading a team and working with cross-functional teams, planning inter-locks with dependent teams, pre-empting the risks and having a plan to mitigate. Experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify high performance IPs and/or SOC designs. Proven track record on driving strategies and successful verification execution on high performance IPs and/or SOC designs. Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools, and infrastructure for high performance-IP and/or VLSI designs is a plus. · Experience with FPGA programming and software is a plus. · Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) are a plus. · Experience with gate level simulation, power aware verification, reset verification, contention checking is a plus. · Prior experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-MK1