WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
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The Role:
The AMD IOHUB Team (part of the NBIO organization) is looking for an ASIC Design Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP design starting from execution.
As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
KEY RESPONSIBILITIES:
- Execution of design tasks to implent RTL features
- Microarchitectural design and RTL implementation of IP features.
- Analyze RTL design for power optimization and timing optimization
- Debugging and bug fixing to ensure high IP quality delivery
- Collaborating with PD team to analyze and fix timing related issues
- Collaborate with Design Verification team to execute on design features Timing Synthesis & Drive Physical implementation
- Participate in design specification and RTL code reviews.
- Understand the functional and performance requirements of the IOHUB within various SOCs
- Effectively communicate with multi-disciplined teams located across the globe
PREFERRED EXPERIENCE:
- Strong ASIC design experience
- Proven RTL design experience on large ASIC development projects
- Knowledge of industry standard synthesis tools, flows and back end timing closure(e.g. Formality, CDC & Linting tools, Design Compiler/FX etc)
- Strong background in Verilog and System Verilog
- Strong analytical skills and attention to detail
- Excellent written and communication skills
- Understanding of the IP integration and interactions within an SOC
- Must be a self-starter and able to independently drive tasks to completion
- Demonstrates the ability to debug issues and quickly identify viable solutions
- Team player with proven leadership skills
ACADEMIC EXPERIENCE:
- Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering
LOCATION: Markham, ON, Vancouver, BC
#LI-TB2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
The Role:
The AMD IOHUB Team (part of the NBIO organization) is looking for an ASIC Design Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP design starting from execution.
As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
KEY RESPONSIBILITIES:
- Execution of design tasks to implent RTL features
- Microarchitectural design and RTL implementation of IP features.
- Analyze RTL design for power optimization and timing optimization
- Debugging and bug fixing to ensure high IP quality delivery
- Collaborating with PD team to analyze and fix timing related issues
- Collaborate with Design Verification team to execute on design features Timing Synthesis & Drive Physical implementation
- Participate in design specification and RTL code reviews.
- Understand the functional and performance requirements of the IOHUB within various SOCs
- Effectively communicate with multi-disciplined teams located across the globe
PREFERRED EXPERIENCE:
- Strong ASIC design experience
- Proven RTL design experience on large ASIC development projects
- Knowledge of industry standard synthesis tools, flows and back end timing closure(e.g. Formality, CDC & Linting tools, Design Compiler/FX etc)
- Strong background in Verilog and System Verilog
- Strong analytical skills and attention to detail
- Excellent written and communication skills
- Understanding of the IP integration and interactions within an SOC
- Must be a self-starter and able to independently drive tasks to completion
- Demonstrates the ability to debug issues and quickly identify viable solutions
- Team player with proven leadership skills
ACADEMIC EXPERIENCE:
- Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering
LOCATION: Markham, ON, Vancouver, BC
#LI-TB2