WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
SOC Front-End Integration engineer
THE PERSON:
The candidate is expected to exhibit good verbal and written communication skills, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas.
KEY RESPONSIBLITIES:
- Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
- Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
PREFERRED EXPERIENCE:
- Familiar with Verilog RTL design and has experience of large digital ASIC project.
- Familiar with RTL quality check, including Lint, CDC (Clock Domain Crossing).
- Familiar with RTL synthesis with Fusion Compiler or Design Compiler.
- Familiar with logic equivalence check with Formality or Conformal.
- Familiar with STA (Static Timing Analysis) with primetime and timing constraint quality check.
- Familiar with front-end EDA tools and flows, including Fusion compiler/Design compiler, Prime Time, Formality/Conformal, Spyglass, 0in-CDC, etc.
- Familiar with Unix/Linux and scripts (TCL, Perl, Python, etc.)
- Fluent English on talking, presentation and writing documents.
- Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
ACADEMIC CREDENTIALS:
- MS degree of EE (5+ years) / BS degree (7+ years). in computer engineering/Electrical Engineering.
LOCATION:
Penang, Malaysia
#LI-HS
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
SOC Front-End Integration engineer
THE PERSON:
The candidate is expected to exhibit good verbal and written communication skills, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas.
KEY RESPONSIBLITIES:
- Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
- Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
PREFERRED EXPERIENCE:
- Familiar with Verilog RTL design and has experience of large digital ASIC project.
- Familiar with RTL quality check, including Lint, CDC (Clock Domain Crossing).
- Familiar with RTL synthesis with Fusion Compiler or Design Compiler.
- Familiar with logic equivalence check with Formality or Conformal.
- Familiar with STA (Static Timing Analysis) with primetime and timing constraint quality check.
- Familiar with front-end EDA tools and flows, including Fusion compiler/Design compiler, Prime Time, Formality/Conformal, Spyglass, 0in-CDC, etc.
- Familiar with Unix/Linux and scripts (TCL, Perl, Python, etc.)
- Fluent English on talking, presentation and writing documents.
- Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
ACADEMIC CREDENTIALS:
- MS degree of EE (5+ years) / BS degree (7+ years). in computer engineering/Electrical Engineering.
LOCATION:
Penang, Malaysia
#LI-HS
#LI-Hybrid