AMD
1 day ago

Senior Silicon Design Engineer (Verification)

Penang, Malaysia

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WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE: 
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/GPU architecture, AMBA(AXI/AHB/APB) bus, LPDDR&GDDR architecture, PCI-E/PCI bus, low power design, virtualization, display, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc. 

 

THE PERSON: 
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas. 

 

KEY RESPONSIBLITIES: 

  • Work with global SOC design team for large scale ASIC chip verification.
  • Responsible for multiple aspects in verification areas and provide technically leadership to the engineering team.
  • Accountable for project delivery. 

 

PREFERRED EXPERIENCE: 

  • Familiar with Unix/Linux environment and good at scripts.
  • Understand the architecture of the chip and functional block being designed.
  • Build C/C++ model for simulation.
  • Build test bench and monitors/scoreboard for DUT using UVM, SV language.
  • Compose test plan and validation vectors to ensure functional completeness.
  • Debug function/performance bugs of graphics chips.
  • LLM prompts expertise is a plus.
  • Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.).
  • RTL coding with Verilog/System Verilog and familiar with C/C++/UVM programming.
  • Full cycle experience of SOC DV from testplan/testbench to final signoff.
  • Should have excellent communication skills (both written and oral).
  • Strong problem-solving skills.

 

ACADEMIC CREDENTIALS: 

  • Major in Electronics and Electrical, Computer Science or related, Master Degree or Bachelor.

 

LOCATION:

Penang, Malaysia

 

#LI-HS

#LI-Hybrid




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/GPU architecture, AMBA(AXI/AHB/APB) bus, LPDDR&GDDR architecture, PCI-E/PCI bus, low power design, virtualization, display, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc. 

 

THE PERSON: 
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas. 

 

KEY RESPONSIBLITIES: 

  • Work with global SOC design team for large scale ASIC chip verification.
  • Responsible for multiple aspects in verification areas and provide technically leadership to the engineering team.
  • Accountable for project delivery. 

 

PREFERRED EXPERIENCE: 

  • Familiar with Unix/Linux environment and good at scripts.
  • Understand the architecture of the chip and functional block being designed.
  • Build C/C++ model for simulation.
  • Build test bench and monitors/scoreboard for DUT using UVM, SV language.
  • Compose test plan and validation vectors to ensure functional completeness.
  • Debug function/performance bugs of graphics chips.
  • LLM prompts expertise is a plus.
  • Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.).
  • RTL coding with Verilog/System Verilog and familiar with C/C++/UVM programming.
  • Full cycle experience of SOC DV from testplan/testbench to final signoff.
  • Should have excellent communication skills (both written and oral).
  • Strong problem-solving skills.

 

ACADEMIC CREDENTIALS: 

  • Major in Electronics and Electrical, Computer Science or related, Master Degree or Bachelor.

 

LOCATION:

Penang, Malaysia

 

#LI-HS

#LI-Hybrid

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