Sr. Silicon Design Engineer (AECG ASCI RTL Design/Integration Engineer)

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER  (AECG ASIC RTL Design/Integration)   THE ROLE: As part of the AECG ASIC/Custom silicon team, you will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. #TogetherWeAdvance   THE PERSON:  As a SOC RTL Integration Engineer/Lead, you will work with chip architects to conceive design, help with architecture/product definition through early involvement in the product life-cycle.   KEY RESPONSIBILITIES:  Work with chip architect to understand architecture concept and high level requirements Convert chip spec to RTL using internal and external IPs Plan and deliver RTL for continuous integration testing Support the verification team to devise appropriate test plans and verification strategy Experience in ASIC/SoC front-end (preferably RTL Verilog and VHDL based) design and methodologies. Earlier experience with SoC Integration , Processor based architectures needed. Self-driven and capable for independent work and independent decision making. Knowledge in frontend design experience on IPs involve processor based sub-system, Serial Standard interfaces, Memory controllers Exposure to Low-power design, System Security considered as added advantage Hands on front-end design of complex multi clock domain blocks Fluency in design & verification languages such as VHDL, Verilog, C and System Verilog. Experience in Spyglass for lint and CDC checks. Experience in synthesis and LEC flow. Experience in identifying and implementing complex ECO in netlist. Defining and debugging timing constraints. Knowledge on Verification Methodologies to actively participate in Debug Analysis. Knowledge about system level flows and interaction with Firmware and Software would be added advantage.   PREFERRED EXPERIENCE:  Experience in leading complex subsystem or SOC level integration, quality cleanup and delivery to DV, physical design teams Strong understanding of SOC globals like clocking, reset, boot and power management flows, low power design techniques, security Expertise with quality checks like CDC, Lint, VCLP, LEC Strong technical engineer who communicates well with great collaboration skills   ACADEMIC CREDENTIALS:  Candidate must have a Bachelor’s degree in Electronics/Electrical Engineering and 5+ years of experience in relevant areas. #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.